1. Field of the Invention
The present invention relates to a plasma display panel (PDP) and, more particularly, to a composition of plasma display panel.
2. Description of the Background Art
In general, a plasma display panel (PDP) device receives much attention as a next-generation display device together with a thin film transistor (TFT), a liquid crystal display (LCD), an EL (Electro-Luminescence) device, an FED (Field Emission Display) and the like.
The PDP is a display device which uses a luminescent phenomenon according to an energy difference made when red, green and blue fluorescent materials are changed from an excited state to a ground state after being excited by 147 nm of ultraviolet rays which are generated as a He+X3 gas or N3+X3 gas is discharged from a discharge cell isolated by a barrier rib.
Thanks to its properties of facilitation in manufacturing from a simple structure, a high luminance, a high light emitting efficiency, a memory function, a high non-linearity, a 160° or larger optical angular field and the like, the PDP display device is anticipated to occupy a 40″ or wider large-scale display device markets.
A structure of the conventional PDP will now be described with reference to FIG. 1.
FIG. 1 is a sectional view showing a structure of a conventional PDP.
As shown in FIG. 1, the conventional PDP includes: a lower insulation layer 20 formed on a lower glass substrate 21; an address electrode 22 formed at a predetermined portion on the lower insulation layer 20; a lower dielectric layer 19 formed on the address electrode 22 and the lower insulation layer 20; an isolation wall 17 defined in a predetermined portion on the lower dielectric layer 19 in order to divide each discharging cell; a black matrix layer 23 formed on the isolation wall 17; a fluorescent layer 18 formed with a predetermined thickness on the side of the black matrix layer 23 and the isolation wall 17 and on the lower dielectric layer 19, and receiving ultraviolet ray and emitting each red, green and blue visible rays; a glass substrate 11; a sustain electrode 12 formed at a predetermined portion on the upper glass substrate 11 in a manner of vertically intersecting the address electrode 22; a bus electrode 12 formed on a predetermined portion on the sustain electrode 12; a first upper dielectric layer 14 formed on the bus electrode 13, the sustain electrode 12 and the upper glass substrate 11; a second upper dielectric layer 15 formed on the first upper dielectric layer 14; and a protection layer (MgO) 16 formed on the second upper dielectric layer 15 in order to protect the second upper dielectric layer 15.
The first and second upper dielectric layers 14 and 15 are called upper dielectric layers.
The operation of the conventional PDP will now be described.
First, as the upper glass substrate 11 and the lower glass substrate 21 of the conventional PDP, an SLS (Soda-Lime Silicate) glass substrate is used.
The lower insulation layer 20 is positioned on the lower glass substrate 21, the SLS glass substrate, and the address electrode 22 is positioned on the lower insulation layer 20.
The lower dielectric layer 19 positioned on the address electrode 22 and the lower insulation layer 20 blocks visible rays emitted toward the lower glass substrate 21.
In order to increase the luminous efficacy, a dielectric layer having a high reflectance is used as the lower dielectric layer 19. The lower dielectric layer 19, a translucent dielectric layer with a reflectance of 60% or above, minimizes loss of light.
The fluorescent layer 18 is formed by laminating in a sequential order of red, green and blue fluorescent materials. A specific wavelength of visible ray is emitted depending on an intensity of an ultraviolet ray according to plasma generated between the isolation walls 17.
Meanwhile, at a lower surface of the upper glass substrate 11, the SLS glass substrate, there are formed the sustain electrode 12 positioned to vertically intersect the address electrode 22 and the bus electrode 13 positioned on the sustain electrode 12. And upper dielectric layers 14 and 15 with an excellent light transmittance are positioned on the bus electrode 13.
The protection layer 16 is positioned on the upper dielectric layer 15 in order to prevent the upper dielectric layer 15 from being damaged due to generation of plasma. Herein, since the first upper dielectric layer 14 is directly contacted with the sustain electrode 12 and the bus electrode 13, it must have a high softening temperature in order to avoid a chemical reaction with the sustain electrode 12 and the bus electrode 13. In addition, since the second upper dielectric layer 15 is expected to have a high smoothness because the protection layer 16 is formed thereon, its softening temperature must be lower by scores of ° C. than the first upper dielectric layer 14.
Commonly, the PDP display device has a problem of jitter occurrence. The jitter phenomenon, which occurs as discharging is delayed for a certain time for a specific applied scan pulse, causes a mis-discharging and interferes a high speed driving.
The jitter phenomenon is affected mainly by a surface state of the protection layer (MgO) and a crystallinity, an electric permittivity (that is, a dielectric constant) and thickness of each layer, a structure and a gap of isolation walls and electrodes, a driving method, a type and a content of a discharging gas, and the like. Especially, Xe has a low diffusion rate in a discharging space, so if the Xe content is increased in order to obtain a high efficacy characteristics, there is higher probability that the jitter phenomenon occurs.
Therefore, in the conventional art, in order to solve the problem of the mis-discharging due to the jitter phenomenon, usually, an electric permittivity of the upper dielectric layer and the lower dielectric layer is increased or their thickness is reduced. In general, the upper dielectric layer and the lower dielectric layer of the PDP has an electric permittivity of about 12˜15 range, and especially, in case of the lower dielectric layer, because it contains TiO2 powders for increasing the reflectance, it has a higher electric permittivity.
However, if the electric permittivity is increased by about twice, a discharge voltage is degraded due to the increase in the capacitance, and thus, about 20% of the overall jitter is reduced.
In addition, the jitter characteristics is also changed due to a change in the thickness of the upper dielectric layer and the lower dielectric layer of the PDP. For example, if the gap between the upper electrodes 12 and 13 and the lower electrode 22 narrows as the thickness of the upper dielectric layer and the lower dielectric layer of the PDP is reduced, the discharge voltage would be dropped and thus the jitter can be reduced.
The lower dielectric layer and the upper dielectric layer are made of a material having PbO as a principal component with an electric permittivity of about 12˜15, and the gap between the upper electrode and the lower electrode is maintained at about 100 μm.
The fabrication method of the lower dielectric layer 19 and the upper dielectric layers 14 and 15 will now be described in detail.
The lower dielectric layer is formed as follows: Mixed powders, in which scores of % of oxide in a powder state such as TiO2 or Al2O3 having a particle diameter of below 2 μm is mixed for improving reflection characteristics and controlling an electric permittivity, is mixed with an organic solvent to produce a paste with a viscosity of about 40000˜50000 cps, and the paste is printed/fired, thereby forming the lower dielectric layer. In this case, the firing temperature is usually at the range of 550˜600° C., and the thickness of the lower dielectric layer is about 20 μm.
The upper dielectric layer is formed as follows: a paste obtained by mixing an organic binder is coated to boro-silicate glass (BSG) powder with a size of a particle diameter of 1 μm˜2 μm and containing about 40% of Pb in a screen printing method, and then, the coated paste is fired at a temperature of 550° C.˜580° C.
Characteristics change in the jitter according to the change in the electric permittivity will now be described with reference to FIGS. 2A and 2B.
FIG. 2A shows jitter occurrence characteristics in case that a distance constant of the upper dielectric layer and the lower dielectric layer for a general PDP is 14, and FIG. 2B illustrates jitter occurrence characteristics in case that a distance constant of the upper dielectric layer and the lower dielectric layer for a general PDP is 25.
As shown in FIGS. 2A and 2B, if the electric permittivity is changed from 14 to 25, an operation speed is increased from 1.25 μs to 1.14 μs due to the increase in the capacitance, and according to which the overall jitter is reduced by about 11%.
However, since a withstand voltage is reduced according to the increase in the electric permittivity, there is a limitation in increasing the electric permittivity of the PbO-based dielectric material (the material of the upper dielectric layer and the lower dielectric layer).
In addition, in the case of increasing the capacitance by reducing the thickness of the material having the same electric permittivity, a problem arises that the conventional dielectric can not withstand the withstand voltage of about 560V.
To sum up, as stated above, the dielectric layer of the conventional PDP has the following problem.
That is, since the dielectric layer is made of the PbO-based dielectric material, if the electric permittivity of the dielectric is increased in order to reduce the jitter, the withstand voltage would be reduced. Thus, the electric permittivity of the dielectric can not be increased to its maximum.
In addition, if the thickness of the upper dielectric layer and the lower dielectric layer is reduced, the withstand voltage would be lowered down, causing the problem that jitter can not be effectively reduced, and thus, a high speed driving is hardly performed.
Other conventional PDPs and their fabrication methods are disclosed in the U.S. Pat. No. 5,838,106 issued on Nov. 17, 1998, a U.S. Pat. No. 6,242,859 issued on Jun. 5, 2001, and a U.S. Pat. No. 6,599,851 issued on Jul. 29, 2003.